Differential drivers are employed for a variety of functions, such as to provide parallel data to serial data conversion. For example, they may be used to convert a parallel 10-bit digital data signal to a serial 1-bit digital data signal. Also, differential drivers may be employed to convert 1-bit serial digital data signal, (e.g., a rail-to-rail digital signal swinging from 0 V to VDD), to a pair of differential analog signals that meet an electrical specification of a transmitter for a relevant signaling standard.
High speed input/output (I/O) interfaces such as serial-ATA (SATA) require a transmitter to meet different rise and fall (rise/fall) time specifications depending on the generation specification they are operating under. The generation one (Gen1) SATA specification requires a 1.5 Gb/s data rate, while the generation two (Gen2) specification requires a 3 Gb/s data rate, and generation three (Gen3) specification requires a 6 Gb/s data rate. At the same time, the transmitter should also meet a maximum of 20 ps differential skew specifications. The transmitter output signal incurs a larger loss on the transmitting channel at the Gen3 data rate than at the Gen1 data rate due to the limited bandwidth of the channel. To compensate for this channel loss, the transmitter has to output a larger amplitude signal at the Gen3 data rate than at Gen1 data rate.
The rise/fall time specification of SATA Gen3 is from 33 ps to 68 ps, Gen2 is from 67 ps to 136 ps, and Gen1 is from 100 ps to 273 ps. At the Gen3 data rate, the transmitter power consumption may be of concern, particularly when multiple lanes of transmitters are running at a high speed at the same time. Therefore, a differential driver that is effective for transmission at one rate may not be as effective at other rates. The two differential drivers that are commonly used are voltage-mode differential drivers and current-mode differential drivers.
A voltage-mode differential driver may be utilized when running at high speeds, such as the SATA Gen3 data rate, because it consumes lower power than a current-mode differential driver. However, when the same voltage-mode differential driver runs at a relatively low speed, such as the SATA Gen1 data rate, which is four times slower than the Gen3 data rate, the drive strength of the voltage-mode driver has to be weakened by many times to slow down the output signals in order to meet the slower rise/fall time requirement of the Gen1 specification.
To weaken the drive strength, the majority of the transistors in a voltage-mode differential driver have to be turned off. The situation then occurs that a small number of turned-on transistors have to drive a large number of turned-off transistors whose parasitic capacitance is not only very large, but also varies a lot across process, voltage, and temperature (PVT) corners. Therefore, the output rise/fall time of the weakened voltage-mode driver may incur a large variation across PVT corners, which may in turn cause a large mismatch between the rise time and fall time, ultimately causing a large differential skew between the two differential output signals. The transmitter may then not be able to simultaneously meet the rise/fall time and differential skew requirements at the low speed.
A current-mode differential driver, on the other hand, may be utilized to handle the rise/fall time variation and differential skew issues at the low speed, because its rise/fall time is determined by a resistive-capacitance (RC) time constant and therefore has less variation across PVT corners than a voltage-mode differential driver. However, the current-mode driver consumes much more power than a voltage-mode driver when running at high speeds such as the SATA Gen3 data rate. In multiple lane applications, the total power consumption becomes so large that the number of lanes that simultaneously run at the Gen3 data rate may have to be limited.
Therefore, it is challenging to both save power at high speed data rates and also meet different rise/fall times and strict differential skew requirements at low speeds. In Giga-bit high speed circuit design, the less the loading, the faster the circuit can run and the less power the circuit consumes. Therefore, a circuit that occupies a smaller area may operate faster and consume less power when running at a specific speed.
Accordingly, it would be beneficial to provide a differential driver that is capable of effectively operating at both a low speed data rate, such as a Gen1 data rate, when required, while also being capable of operating at a higher speed data rate, such as a Gen2 or Gen3 data rate when required.